Arm Newsroom Blog
Blog December 20, 2023

How Can Strategic AI Chip Development Accelerate the Future of Technology?

Strategic collaboration accelerates Custom Silicon for evolving AI workloads
By Kevork Kechichian, EVP, Solutions Engineering, Arm

As AI continues its rapid evolution, optimized silicon is crucial to unlock next-generation applications. Arm serves as a foundation for this innovation with its CPU, GPU and related technologies and pioneering solutions like the Arm Neoverse Compute Subsystems (CSS), introduced earlier this year.

CSS are validated and performance-optimized subsystems – building blocks seamlessly integrated into systems-on-chip (SoCs) – designed to mitigate risk, reduce non-recurring engineering (NRE) costs, and expedite the time to market. Neoverse CSS gives partners the flexibility needed to take these building blocks, tailor them for cutting-edge process nodes, and enable access to custom acceleration for new AI applications. Considering the increased complexity of CSS and the level of expertise needed to assemble a competitive CSS, software is a critical component of each delivery, from drivers all the way to the application layer, with partner-specific workloads used to optimize performance and power.

This process involves taking Arm Neoverse platform IP and refining it for enhanced performance, power efficiency, and area optimization, using a state-of-the-art foundry processes. This initiative is an integral part of Arm Total Design, an ecosystem program designed to smooth and speed delivery of customized SoCs, a critical aspect in the era of AI.

How Does Collaboration Accelerate AI-Driven SoC Development?​

But delivering on the promise of transformative AI applications isn’t done in a vacuum. Helping the industry overcome those high-level design and implementation challenges is our longtime prime EDA partner Cadence, which joined Arm Total Design as an exclusive EDA partner to accelerate the development of custom SoCs based on Neoverse CSS. As part of this collaboration, Arm and Cadence customers can accelerate their SoC design process through access to Cadence’s full-flow system-level design verification and implementation solutions. 

The Cadence full-flow digital design, verification, and design IP solutions are being validated for Neoverse CSS, including the Cadence Joint Enterprise Data and AI (JedAI) platform and generative AI-based solutions, which includes the Cadence Cerebrus Intelligent Chip Explorer and Verisium AI-Driven Verification Platform. Additionally, mutual customers will have access to turnkey Cadence Design Services to take Arm-based systems from concept to tapeout, helping achieve first-pass silicon success.

Why is the AI Chip Era Catalyzing a Shift in Computing Power and Efficiency?

Part of the reason is that mounting technological complexity I referenced earlier. But also, in the age of AI, Omdia Research indicates that 85 percent of CPU cycles and compute cycles in the data center will actually be driving inference, which is still at its infancy in terms of being able to be run at scale. We want to be able to have inferencing run not only in cloud data centers, but also in edge devices, and even in the mobile devices that many of you are carrying today.

It’s been Arm’s mission to unlock a broader ecosystem of customized silicon that can be used to build this kind of hardware for not only specialized workloads but to address the insatiable power budgets in data centers. Indeed, compute can only scale if the power can be harnessed efficiently, and Neoverse CSS was created to enable scale.

We’re working with Cadence in many areas, but there are three that stand out now:

  • SystemReady pre-silicon verification
  • EDA workloads on Arm Neoverse
  • Future technologies

With each, the fundamental goal is to make the lives of innovators easier and more efficient to drive new innovation into the market.

How Will AI Chip Integration in SystemReady Specifications Revolutionize Pre-Silicon Verification?​

With SystemReady – a set of specifications that enable partners to quickly and easily run existing software directly on their hardware – Arm is working with Cadence on pre-silicon verification tools that ensure that silicon will be SystemReady-compliant out of the gate. This will ensure that when customers develop products, those products work on the first try.

Cadence EDA tools running on, say, Neoverse-based AWS Graviton2 instances deliver up to 40 percent TCO improvement over traditional architectures. That number, 40, is not a typo.

Cadence has already ported Xcelium, Liberate, Spectre, and JasperGold, and the results are astonishing. Comparing performance and cost on AWS Graviton 3 versus Graviton 2, Xcelium performance is up 22% while cost is down 12%; Liberate 33% performance gain and 21% cost reduction; Spectre 35%/22%; and JasperGold 30%/18%.

In fact, Arm already uses these tools internally to verify our next-generation Neoverse IP cores. You can see a virtuous cycle, can’t you?

And finally, Arm is excited to continue working with Cadence on future technologies. A great example is the work that we’re doing together on the Cadence Cerebrus AI products, which help engineers achieve optimal design power, performance, and area with a fraction of the effort. These products enable us to go off and do things like simulate and validate Arm Neoverse V2 cores that are pushing 3nm and beyond. 

How Does the AI Chip Revolution Impact the High Stakes of Silicon Development?​

Arm and Cadence have a unique and special partnership which is critical as developing silicon on a leading-edge process like 2nm can cost $500-$700 million per project involving the silicon and the software costs of developing that project. So placing bets on silicon is an enormous decision for a lot of cloud operators and OEMs today. Our partnership together ensures that we will do everything possible together to maximize the return.

The age of AI demands a faster, safer path to custom silicon, and there are generally three ways to realize SoCs:

  • Via third-party IP integration
  • Full-custom chips
  • Compute subsystems

The first two paths come with high development efforts and costs, long turn-around times (which are intolerable in a fast-changing market) and considerable risk. But compute subsystems afford innovators a speedy path marked by affordable costs and reasonable effort, short turn-around times and low risk. 

That’s the kind of design environment and desired outcomes that only the Arm and Cadence partnership can deliver. 

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By Kevork Kechichian, EVP, Solutions Engineering, Arm
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