Alphawave Semi and Arm Accelerate Scalable Computing with CSA-Compliant Chiplets

This blog was written by Shivi Arora, Director , ASIC IP Solutions, and Sue Hung Fung, Principal Product Marketing Manager, Alphawave Semiconductor.

As computing demands for HPC, AI/ML, and cloud infrastructure grow, modular architectures are replacing traditional monolithic System-on-Chip (SoC) designs. These legacy designs are increasingly expensive and difficult to scale due to ever increasing silicon complexity. In response, the industry is embracing chiplet-based System-in-Package (SiP) solutions, which reduce production costs, enhance yield, and enable flexible system integration. Arm® Chiplet System Architecture (CSA) plays a pivotal role in standardizing this transition, ensuring seamless integration of compute chiplets, high-performance accelerators, and memory. This evolution paves the way for more scalable, efficient, and adaptable compute infrastructure.

Multi-chiplet architectures need a standard coherent interconnect from the processor (the compute element) to the accelerator. Full cache coherency is required between CPU cores, accelerators, and other components to share data efficiently without redundant memory copies. Datacenters and cloud computing need multi-core and multi-socket scalability. 

Arm is creating a standards-based foundation for building solutions with Arm Neoverse™ Compute Subsystems (CSS), which Alphawave Semi is helping to enable as an Arm Total Design partner. The basic building blocks can be built with chiplets, accelerators, CPUs, and leverage a robust foundation for integration relying on industry standards. Based on this modular chiplet approach, two or more Arm compute chiplets can be integrated in a package. This allows for modular expansion of compute multi-core counts on a larger compute platform.

Neoverse CSS leverages industry guidance and standards with Chiplet System Architecture (CSA) and AMBA CHI C2C. CSA defines chiplet types and chiplet definitions, and defines their integration and connectivity. AMBA CHI C2C defines a cache coherency standard, and facilitates coherent communication between an Arm Neoverse compute die and an accelerator, ensuring high bandwidth and optimized data movement. Alphawave Semi adheres to these two industry standards which are critical for a standardized interface for system expansion. 

The AMBA CHI C2C is a high-performance interconnect protocol designed for enabling efficient communication between compute and accelerator chiplets. Alphawave Semi leverages this standard for its compute based chiplet architecture to achieve low-latency, high-bandwidth communication to the accelerator. The CSA provides a structured framework for defining chiplet integration to ensure consistency across different chiplet implementations of I/O, memory, and compute units. CSA allows system architects to maintain coherency, security, and efficient synchronization across multiple interconnected chiplets.  

By implementing CSA, Alphawave Semi can map different system components based on interface types, ensuring that all chiplets communicate efficiently. The CSA specification defines clear boundaries and responsibilities for system partitioning. Security and system controller synchronization ensure data integrity across chiplets. Interrupt and debug access management allow for effortless debug and issue resolution. System counter synchronization maintains timing consistency across different chiplets.

Alphawave Semi supports standardized and proprietary interfaces on their SiP architectures. These include widely used UCIe, PCIe, and SerDes. Chiplet expansion with AMBA CHI C2C allows efficient interconnects between the compute and accelerator components. By leveraging the interconnect technology of AMBA CHI C2C, the protocol packetization and data link layers remain efficient while utilizing this transport mechanism. The Alphawave Semi compute chiplet can then operate cohesively with the accelerator while achieving high-performance scalability. 

One major challenge in accelerator-based infrastructure solutions is the need for a high bandwidth link between host and accelerator. Large bandwidth is required to enable seamless data transfer. AMBA CHI C2C facilitates efficient link aggregation to achieve this high performance using PCIe or UCIe transport layers. Integration with PCIe or CXL infrastructure can be used for control path communication. AMBA CHI C2C enables optimized data flow with load balancing across multiple links. It has relaxed ordering rules for improved efficiency, and extended system capabilities including MPAM (Memory Partitioning and Monitoring) for accelerators. 

Alphawave Semi’s Arm Neoverse-based chiplets, leveraging AMBA CHI C2C, provide a highly efficient, scalable, and standards-based solution for modern compute infrastructure challenges. Using an Arm-approved system architecture ensures reliable communication from the host to accelerator. System developers can continue to use a familiar existing software framework such as Arm’s system software, reducing the need for extensive rewrites, and ensuring minimal disruption when adapting software for new hardware architecture. Software teams will be able to use operating systems and software framework optimized for the Arm architecture, which can run with minimal modification. This creates an ideal foundation for next-generation computing architectures in AI, cloud, and HPC environments. 

Using Alphawave Semi’s Arm Neoverse-based Compute chiplets, the latest advancements in chiplet integration and accelerator attach can be optimized. Arm and Alphawave Semi are driving the future of modular compute architectures, enabling next-generation AI, cloud, and high-performance computing through open standards and scalable designs.

Learn More:

Explore Alphawave Semi’s advanced chiplet solutions, as well as more information about Arm Neoverse CSS.