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Neoverse V1: A New Approach to HPC

Brent Gorda explores the Arm Neoverse V1 CPU, designed to deliver leading per-core performance on demanding HPC and AI/ML-assisted workloads
By Brent Gorda, Senior Director, HPC , Arm
Data Center

With the right set of ingredients, you can accomplish almost anything. Indeed you can change the world. 

The chromatic musical scale consists of only twelve notes, but it’s the backbone for compositions ranging from Beethoven’s Ninth Symphony to the Old Spice jingle. DNA? Four amino acids.

This truism rules the technology industry as we’ve all witnessed. Sectors such as PCs and solar power took flight after developers created a portfolio of modular, flexible and continually improving components that could be used to build more sophisticated systems. Technology democratization also opened the door for more participants.

At Arm, we strive to embed these principles in our work.  Look at Neoverse V1, Arm’s first processor for technical workloads and the HPC community for example. From a design point, the driver was to deliver the building blocks for exascale computing.  At the same time, we sought to provide designers with many degrees of freedom so they could target specific use cases like drug discovery or weather simulation or subsequently retrofit their designs for different projects down the road.

Innovation Inside

The key is the flexibility of Arm’s business model and IP. By providing the building blocks for exascale processors while leaving enough room to customize, our partners can innovate inside the chip itself – something unheard of in the past.  With many degrees of freedom (knobs and dials) available and standard compliant interfaces, our silicon partners can add their own logic next to the CPU, on the on-chip network (called CMN-700) as well as via standard interfaces such as CXL, CCIX & PCIe.

Additionally, the combination of customization and compatibility ensures that the wider software developer community will be there for them. Over the past few years, the leading developers of CI/CD tools, containers, libraries, security and other services have gravitated toward Arm as the Arm HPC community has grown. Similarly, this growing portfolio of tools and applications reduce the risk for groups debating the plunge and the process becomes a positive feedback loop.

The response from our partners to date has been incredibly gratifying. SiPearl, part of the European Processor Initiative, has announced it will use Neoverse V1 at the heart of its Rhea SoC slated for the 2022 time frame. A Rhea-based with custom accelerators also designed in the EU is expected to first appear in exascale systems and trickle down over time to cloud servers, autonomous cars and other markets.

In the Republic of Korea, the Electronics and Telecommunications Research Institute (ETRI) is developing an exascale-class CPU called K-AB21 aimed at achieving 1,600 teraflops per rack and 16 teraflops per CPU. ETRI’s goal for its Neoverse V1-based SoC that will power K-AB21 is to produce a device that can deliver a 2.5x increase in performance over current equivalent-class processors while reducing relatively power consumption by 60%.

Like Rhea, ETRI’s processor will also ultimately migrate to cloud and edge systems.

MEITY C-DAC, the Center for Development of Advanced Computing in the Ministry of Electronics and Information Technology for the Government of India, also recently announced it will build an exascale system with Neoverse V1-based SoCs. Others are on the way.

Performance, Practicality and Flexibility

So what did we include in V1? Our Neoverse V1 provides a 50% uplift in IPC performance over Neoverse N1, which is a general purpose infrastructure server processor that also does quite well on HPC. Neoverse V1 is also our first release to Scalable Vector Extension (SVE) for accelerating HPC, ML and AI-intensive workloads, which account for a growing percentage of HPC workloads.  The SVE technology was built in collaboration with Fujitsu Japan who built the current fastest supercomputer – Fugaku located at the RIKEN Computing Center.  In their design (which is not Neoverse by the way), they added HBM2e, which raised the bar on memory performance to a peak of over 1 terabyte per second.

The Neoverse V1 cores are networked on chip with our coherent mesh network, CMN-700. The network is used to connect CPUs, memory, accelerators and other assets, to increase throughput and performance. CMN-700 provides up to 3TB/s bandwidth, 2.5x more than its predecessor CMN-600. CMN-700 also enables the implementation of high-bandwidth memory systems, coupling the capacity of DDR5 with the bandwidth of HBM. Current Neoverse V1 designs are slated to be produced on 7- and 5-nanometer processors, the most advanced processes currently available.

Every few years, HPC seems to undergo an irreversible architectural due to a technical breakthrough or changes in underlying customer demand. In the 1950s, vacuum tubes gave way to transistors. In the 90s, classic vector systems were supplanted by systems composed with standard processors and components. In the mid-2000s, NVIDIA launched the then novel idea of incorporating GPUs into HPC systems: now, over 2/3rds of the systems in the Top 500 list feature its technology.  There is a clear trend toward accelerated computing in HPC, despite the world’s fastest computer being a CPU-only design.

We seem to be at the start of another one of those periods. Call it the start of the with customers demanding both high performance along with low power, low cost, versatility and compatibility. While I can’t predict exactly what tomorrow’s architectures will look like, I am fairly certain that the underlying ingredients that get us there will be different than the ones we use today.

This article originally appeared on HPC Wire.

A Revolution in High Performance Computing

The Neoverse V1 CPU is designed to deliver leading per-core performance on demanding HPC, HPC in the cloud and AI/ML-assisted workloads. Neoverse V1 is also the first Neoverse processor to include Scalable Vector Extension (SVE) for maximum vector performance, HPC code re-use, and longevity.

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